IJERGS · Volume 2, Issue 5 · September-October 2014 Edition
LOW POWER DESIGN OF JOHNSON COUNTER USING DDFF FEATURING EFFICIENT EMBEDDED LOGIC AND CLOCK GATING
| Journal | International Journal of Engineering Research and General Science (IJERGS) |
|---|---|
| ISSN | 2091-2730 |
| Volume | 2 |
| Issue | 5 |
| Edition | September-October 2014 Edition |
| Year | 2014 |
| Pages | page 572-579 |
| Publisher | P&R Publication |
How to cite
Chandra shekhar kotikalapudi, Smt. P. Pushpalatha (2014). LOW POWER DESIGN OF JOHNSON COUNTER USING DDFF FEATURING EFFICIENT EMBEDDED LOGIC AND CLOCK GATING. International Journal of Engineering Research and General Science, 2(5), 572-579. ISSN 2091-2730. https://www.ijergs.org/article/v2-i5-70.html